Sudhakar Yalamanchili

Sudhakar Yalamanchili

Regents Professor &
Joseph M. Pettit Professor

image004The School of Electrical and Computer Engineering
Georgia Institute of Technology
Mailing Address:

266 Ferst Drive, KACB 2316
Atlanta, GA 30332-0765

Phone: (404) 894-2940
Fax: (404) 894 9959
Office: KACB 2316

Email: sudha@ece.gatech.edu
Weekly Schedule: TBD
Office Hours Spring 2017: Meetings by Appointment
Research: Computer Architecture and Systems Laboratory

Sudhakar Yalamanchili received the B.E degree in Electronics from Bangalore University, India and the Ph.D degree in Electrical and Computer Engineering from the University of Texas at Austin in 1984. He is currently a Regents Professor and Joseph M. Pettit Professor of Computer Engineering in the School of Electrical and Computer Engineering at the Georgia Institute of Technology in Atlanta GA. Prior to joining Georgia Tech in 1989 he was Senior and then Principal Research Scientist at the Honeywell Systems and Research Center in Minneapolis. At Honeywell he was the Principal Investigator for projects in the design and analysis of multiprocessor architectures for embedded applications. During that time he served as a member of Honeywell’s Program Technical Advisory Board to MCC and was an Adjunct Faculty and taught in the Department of Electrical Engineering at the University of Minnesota. He currently serves as a Co-Director Center for Experimental Research in Computer Systems (CERCS) (www.cercs.gatech.edu).

Dr. Yalamanchili contributes professionally with regular service on editorial boards and conference & workshop program committees. Current and recent service includes the Editorial Board of Computer Architecture Letters (2011- 2015), Program Co-Chair for  IEEE/ACM International Symposium on Networks on Chip (2014), and  IEEE International Symposium on Workload Characterization (2015), and Program Committees for IEEE/ACM Supercomputing (2017), the IEEE/ACM International Symposium on Microarchitecture (2015), IEEE International Symposium on High Performance Computer Architecture (2014), and IEEE/ACM International Symposium on Computer Architecture (2014). He is a member of the ACM and an IEEE Fellow.

Research

Our current research interests are organized along the following major themes.

  • Modeling and Simulation technologies for many core architectures and systems. A collaborative project with several faculty, the Manifold project, seeks to develop an open source infrastructure for workload-driven full system parallel simulation of many core architectures. This includes i) KitFox – an open source multiphysics library of public domain tools for integrated energy/power, reliability, cooling, and thermal modeling,  and ii) QSim –  a QEMU based  multicore front-end to drive timing models with current support for  x86-64 and ARM64. Other projects include Eiger(automated model construction), eAudit (energy profiling of applications). ...more
  • Heterogeneous Computing developing compiler and microarchitecture optimizations in support of dynamic parallelism in bulk synchronous applications. We are also working with LogicBlox Inc. developing Red Fox – a compilation environment from Datalog to large-scale multi-GPU clusters including out of core data sets.  Past projects include Oncilla (global address support for GPU clusters), Ocelot (dynamic multiplatorm compilation for CUDA), and Lynx (dynamic code manipulation for BSP programs). ...more
  • Near Data Processing: In collaboration with colleagues, the Cymric project is developing a C++  based tool chain for the generation of synthesizable GPU and RISC microarchitectures for memory-side acceleration. The first generation heterogeneous processors are being targeted for integration into 3D memory systems using the Hybrid Memory Cube (HMC) accompanied by C-based compiler support. The initial target application domains are query processing over large data sets and neuromorphic computing . ...more
  • Power & Thermal Management: This theme  has two components. The first is the development and implementation of rigorous control-theoretic models for power and thermal management in collaboration with Systems & Control faculty. The second investigates tighter physical dependencies between i) the physics (e.g., thermal fields and device wear-out), ii) the operation of the microarchitectural components in terms of delay, reliability, & energy, and iii) packaging (2D, 2.5D, 3D) and cooling (microfluidics) technologies.  This effort utilizes the KitFox library integrated with Manifold models for 2D, 2.5D, and 3D full system architecture modeling. …more

We gratefully acknowledge the generous support of our current and recent research efforts by the National Science Foundation, Sandia National Laboratories, Laboratory for Physical Sciences, SRC, LogicBlox Corporation, Samsung Corporation, HP Labs,  AMD,  Intel Corporation, IBM Corporation, Qualcomm, and NVIDIA Corporation.

Academic

In the recent past I have taught or am teaching the following classes.

ECE 3056: Architecture, Concurrency and Energy in Computations
ECE 8823: GPU Architectures
ECE 8813a: Design and Analysis of Multiprocessor Interconnection Networks

In the past I have devoted time to the development of the following textbooks.

Interconnection Networks, J. Duato, S. Yalamanchili, L. Ni, Morgan Kaufman, 2003.
VHDL Starters Guide, 2nd Edition, Prentice Hall, 2004.
 VHDL: From Simulation to Synthesis, Prentice Hall, 2000 (reprinted in Japanese, 2002)

Problems with this page? Please contact: Sudhakar Yalamanchili at sudha@ece.gatech.edu