VHDL: From Simulation to Synthesis

VHDL: From Simulation to Synthesis

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Publisher: Prentice Hall , ISBN-10: 813170633, ISBN-13: 978-8131706336
Copyright: 2008

This text focuses on presenting the basic features of the VHDL language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by familiarity with digital logic circuits with simulation and synthesis presented as complementary design processes. Field programmable gate arrays are used as the medium for synthesis laboratory exercises and tutorials are provided for the use of the new integrated design environments from Xilinx which is available with the text. The text is targeted for use in sophomore and junior level courses in digital logic and computer architecture.


Text Materials
The following materials are provided for use with the text.  For each chapter below you will find a brief description  and slides for that chapter (PDF).

Chapter 1: Introduction [pdf)]
This chapter provides a very brief introduction to the place hardware description languages employ in a typical digital system design flow. Describes the genealogy of VHDL.

Chapter 2 : Modeling Digital Systems [pdf]
Individual VHDL language constructs can be related to digital system concepts that we are already familiar with. This chapter list fundamental physical and behavioral  attributes of  digital systems. Language constructs to describe each attribute will be introduced in subsequent chapters.

Chapter 3: Simulation vs. Synthesis [pdf]
Simulation and synthesis are two complementary design activities: the former is descriptive while the latter is prescriptive. Understanding key attributes of each activity is necessary to understand how hardware description languages such as VHDL can be applied in the course of each activity.

Chapter 4: Basic Language Concepts: Simulation [pdf]
Basic language constructs are introduced by associating each with a physical or behavioral attribute of digital systems. Existing knowledge of digital systems is naturally transformed into executable VHDL descriptions.

Chapter 5: Basic Language Concepts: Synthesis [pdf]
When viewed as a prescription for deriving or synthesizing digital hardware, these same language constructs from Chapter 4 now acquire additional semantics.

Chapter 6: Modeling Behavior: Simulation [pdf]
In describing very large systems we often wish to abstract or hide the details of digital logic implementation while preserving the external behavior. Such a modeling approach can be achieved in VHDL with higher level language constructs structured in processes.

Chapter 7: Modeling Behavior: Synthesis [pdf]
How is hardware inferred from high level descriptions described in Chapter 6, as opposed to inference from the constructs introduced in Chapter 4? Basic inference rules employed by modern VHDL synthesis compilers are reviewed to enable users to develop a consistent set of expectations with regard to how hardware is generated from high level VHDL language constructs.

Chapter 8: Modeling Structure [pdf]
The use of hierarchy and abstraction is necessary to handle large designs and consequently requires the introduction of  new language constructs. A hierarchy of netlists is a standard representation in traditional digital design  tools and VHDL provides language constructs for a textual description of such a hierarchy.

Chapter 9: Subprograms, Packages, and Libraries [pdf]
Abstraction is enabled in VHDL via standard programming language concepts such as procedures, functions, packages and libraries to enable design re-use, sharing, and maintenance.

Chapter 10: Basic Input/Output [pdf]
Binary and text file input/output mechanisms are used to enable the integration of the results of test generation tools and the VHDL models under test. Basic error checking and testbench generation techniques are also covered.
Chapter 11:  Programming Mechanics [pdf]
This chapter provides an intuition about the practical aspects of VHDL environments: the terminology and mechanics of organizing, building, simulating, and synthesizing VHDL models.

Chapter 12: Identifiers, Data Types, and Operators [pdf]
A quick reference guide to the basic language syntax.

References [pdf]
References to some excellent texts that cover more advanced features of the language.

Synthesis Hints [pdf]
This is a summary of basic inference rules and the effect on the resulting synthesized hardware.

Starting Program Template [pdf]
A program template illustrating the syntactical relationships between various VHDL constructs. A handy reference early in process of learning VHDL.

Modeling Recommendations[pdf]
Suggestions and hints for constructing models.


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